1. Field of the Invention
The present invention relates to a technology for reading data from a main memory at higher speed, and more particularly to a technology for using a cache memory for acceleration.
2. Description of the Related Art
In recent years, processors have been improved dramatically in the operating frequency. In contrast, dynamic random access memories (DRAMS) typically used as main memories have not been so much improved in the operating frequency as the processors. Taking advantage of the processor performances thus requires some contrivance. The access times of the main memories have been reduced by using the technique of interposing a cache memory between a main memory and a processor.
Nevertheless, even if the processor accesses the cache for a designated address, the cache does not always contain the desired data. In such cases, a cache miss occurs to require a refill from the main memory. When cache misses like this occur frequently, the cache not only tails to contribute to acceleration but also causes overhead.